D-10-18 An Approach to Temperature Control During VLSI Test

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Classification of Sequential Circuits Based on τ^k Notation and Its Applications(VLSI Systems)
Design and Optimization of Transparency-Based TAM for SoC Test
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
D-10-18 An Approach to Temperature Control During VLSI Test
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
Scheduling Power-Constrained Tests through the SoC Functional Bus
NoC Wrapper Optimization under Channel Bandwidth and Test Time Constraints
Power-Conscious Microprocessor-Based Testing of System-on-Chip
Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)
Program-Based Delay Fault Self-Testing of Processor Cores
Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
Program-Based Delay Fault Self-Testing of Processor Cores
SPIRIT: A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (ディペンダブルコンピューティング)
Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)
Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
Power constrained IP core wrapper design with partitioned clock domains (VLSI設計技術)
Power constrained IP core wrapper design with partitioned clock domains (信号処理)
FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
Optimal Granularity of Parallel Test Generation on the Client-Agent-Server Model
SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
SPIRIT:A High Robust Combinational Test Generation Algorithm (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)
Preemptive System-on-Chip Test Scheduling(SoC Testing)(Test and Verification of VLSI)
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch(Dependable Computing)
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips(Dependable Computing)
Effect of BIST Pretest on IC Defect Level(Dependable Computing)
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST(Dependable Computing)
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
A New Class of Sequential Circuits with Acyclic Test Generation Complexity(メモリテイストとテスト生成複雑度,VLSI設計とテスト及び一般)
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths(Dependable Computing)
A Low Power Deterministic Test Using Scan Chain Disable Technique
Design and Optimization of Transparency-Based TAM for SoC Test
Fault set partition for efficient width compression
On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing
Non-scan Design for Single-Port-Change Delay Fault Testability
Delay Testing: Improving Test Quality and Avoiding Over-testing
On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing

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