On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing

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概要

• 論文の詳細を見る
• 2012-06-15

著者

• Inoue Michiko

  Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

• Yoneda Tomokazu

  Nara Institute Of Science And Technology

• Yoneda Tomokazu

  Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

• HATAYAMA Kazumi

  Nara Institute of Science and Technology

• YAMATO Yuta

  Nara Institute of Science and Technology

関連論文

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• Power-Conscious Microprocessor-Based Testing of System-on-Chip
• Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)
• Program-Based Delay Fault Self-Testing of Processor Cores
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• Program-Based Delay Fault Self-Testing of Processor Cores
• Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
• Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
• Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (システムLSI設計技術・デザインガイア2007--VLSI設計の新しい大地を考える研究会)
• Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (ディペンダブルコンピューティング)
• Thermal-aware test scheduling with cycle-accurate power profiles and test partitioning (VLSI設計技術)
• Power constrained IP core wrapper design with partitioned clock domains (回路とシステム)
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• Power constrained IP core wrapper design with partitioned clock domains (信号処理)
• A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips(Dependable Computing)
• Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
• Design and Optimization of Transparency-Based TAM for SoC Test
• On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing
• Non-scan Design for Single-Port-Change Delay Fault Testability
• Delay Testing: Improving Test Quality and Avoiding Over-testing
• On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing

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