Program-Based Delay Fault Self-Testing of Processor Cores
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概要
- 論文の詳細を見る
- 2003-11-21
著者
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Fujiwara H
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Singh Virendra
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Inoue Michiko
The Authors Are With The Nara Institute Of Science And Technology (naist)
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Inoue Michiko
Nara Institute Of Science And Technology:japan Science And Technology Agency Crest
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SALUJA Kewal
University of Wisconsin-Madison
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SALUJA Kewal
The author is with the University of Wisconsin-Madison
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Singh Virendra
Nara Institute of Science & Technology
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FJIWARA Hideo
Nara Institute of Science & Technology
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Inoue Michiko
Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn
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Saluja K
Department Of Electrical And Computer Engineering University Of Wisconsin-madison
関連論文
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- Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
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- Delay Fault Testing of Processor Cores in Functional Mode(Dependable Computing)
- Program-Based Delay Fault Self-Testing of Processor Cores
- Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- Program-Based Delay Fault Self-Testing of Processor Cores (デザインガイア2003--VLSI設計の新しい大地を考える研究会)
- Program-Based Delay Fault Self-Testing of Processor Cores
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- Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
- Non-scan Design for Single-Port-Change Delay Fault Testability
- On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing