Design and Optimization of Transparency-Based TAM for SoC Test

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概要

• 論文の詳細を見る

• We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.

• 2010-06-01

著者

• YONEDA Tomokazu

  Nara Institute of Science and Technology (NAIST)

• SHUTO Akiko

  Hiroshima City University

• ICHIHARA Hideyuki

  Hiroshima City University

• INOUE Tomoo

  Hiroshima City University

• FUJIWARA Hideo

  Nara Institute of Science and Technology (NAIST)

• Yoneda Tomokazu

  Nara Inst. Sci. And Technol. (naist) Ikoma‐shi Jpn

• Fujiwara Hideo

  Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn

• Inoue Tomoo

  Hiroshima City Univ. Hiroshima‐shi Jpn

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