Imai Masaharu | Osaka University
スポンサーリンク
概要
関連著者
-
Imai Masaharu
Osaka University
-
Takeuchi Yoshinori
Osaka University
-
SAKANUSHI Keishi
Osaka University
-
FUJIWARA Hideo
Nara Institute of Science and Technology (NAIST)
-
Kumura Takahiro
NEC Corporation
-
Taga Soichiro
Kwansei Gakuin University
-
Ishiura Nagisa
Kwansei Gakuin University
-
Onodera Hidetoshi
Kyoto Univ. Kyoto‐shi Jpn
-
Imai Masaharu
Graduate School Of Information Science And Technology Osaka University
-
Shirakawa Isao
Osaka University
-
Yasuura Hiroto
Department Of Computer Science And Communication Engineering Kyushu University
-
Yasuura Hiroto
Department Of Computer Science And Communication Engineering Graduate School Of Information Science
-
Yamauchi Hideki
Osaka University:microelectronics Research Center Sanyo Electric Co. Ltd.
-
Sakanushi K
Graduate School Of Information Science And Technology Osaka University
-
Takeuchi Yoshinori
Graduate School Of Information Science And Technology Osaka University
-
Akino Toshiro
Matsushita
-
Gajski Daniel
University of California
-
Sasao Tsutom
Kyushu Institute of Technology
-
Sato Masao
Waseda University
-
Saucier Gabriele
Institut National Polytechnique de Grenoble
-
Fujiwara Hideo
Nara Inst. Of Sci. And Technol. (naist) Ikoma‐shi Jpn
-
Taniguchi Ittetsu
Graduate School Of Information Science And Technology Osaka University
-
Wakabayashi Shin'ichi
Hiroshima Univ.
-
Fujiwara Hideo
Nara Institute Of Technology
-
Yasuura Hiroto
Department Of Computer Science And Communication Engineering Graduate School Of Information Science
-
TANIGUCHI Ittetsu
Ritsumeikan University
-
KOBAYASHI Ayataka
Osaka University
-
Masaharu Imai
Osaka University
-
Iwato Hirofumi
Osaka University
著作論文
- Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors
- FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
- VLSI Architecture for Real-Time Fractal Image Coding Processors (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
- Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design
- A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions