VLSI Architecture for Real-Time Fractal Image Coding Processors (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes an efficientarchitecture for fractal image coding processors. The proposed architecture achieves high-speed image coding comparable to conventional JPEG processing. This architecture achieves less than 33.3 msec fractal image compression coding against a 512×512 pixel image and enables full-motion fractal image coding. The circuit size of the proposed architecture design is comparable to those of JPEG processors and much smaller than those of previously proposed fractal processors.

• 社団法人電子情報通信学会の論文
• 2000-03-25

著者

• Takeuchi Yoshinori

  Osaka University

• Imai Masaharu

  Osaka University

• Yamauchi Hideki

  Osaka University:microelectronics Research Center Sanyo Electric Co. Ltd.

関連論文

• Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors
• Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems
• Reconfigurable AGU : An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors
• FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
• Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram(System Level Design,VLSI Design and CAD Algorithms)
• VLSI Architecture for Real-Time Fractal Image Coding Processors (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
• Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
• Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design
• A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions

スポンサーリンク