Takeuchi Yoshinori | Osaka University
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概要
関連著者
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Takeuchi Yoshinori
Osaka University
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Imai Masaharu
Graduate School Of Information Science And Technology Osaka University
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Takeuchi Yoshinori
Graduate School Of Information Science And Technology Osaka University
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Masaharu Imai
Osaka University
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Imai Masaharu
Osaka University
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Sakanushi K
Graduate School Of Information Science And Technology Osaka University
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Takeuchi Yoshinori
Graduate School Of Engineering Science Osaka University
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Imai Masaharu
Graduate School of Electrical and Electronic Engineering Kogakuin University
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SAKANUSHI Keishi
Graduate School of Information Science and Technology, Osaka University
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TAKEUCHI Yoshinori
Graduate School of Information Science and Technology, Osaka University
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IMAI Masaharu
Graduate School of Information Science and Technology, Osaka University
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SAKANUSHI Keishi
Osaka University
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Taniguchi Ittetsu
Graduate School Of Information Science And Technology Osaka University
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Tanaka Hiroaki
Department Of Information Systems Engineering Graduate School Of Information Science And Technology
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YOUNESS Hassan
Graduate School of Information Science and Technology, Osaka University
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SALEM Ashraf
Faculty of Engineering, Ain Shams University
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WAHDAN Abdel-Moneim
Faculty of Engineering, Ain Shams University
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TAKEUCHI Yoshinori
Department of Media Science, Graduate School of Information Science, Nagoya University
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Kumura Takahiro
NEC Corporation
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Taga Soichiro
Kwansei Gakuin University
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Ishiura Nagisa
Kwansei Gakuin University
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Imai Masaharu
Department Of Information And Computer Sciences Toyohashi University Of Technology
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Salem Ashraf
Faculty Of Engineering Ain Shams University
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Youness Hassan
Graduate School Of Information Science And Technology Osaka University
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Jayapala Murali
Imec Vzw.
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TANIGUCHI Ittetsu
Graduate School of Information Science and Technology, Osaka University
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RAGHAVAN Praveen
IMEC vzw.
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CATTHOOR Francky
IMEC vzw.
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TANAKA Hiroaki
Graduate School of Engineering, Tohoku University
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Yamauchi Hideki
Osaka University:microelectronics Research Center Sanyo Electric Co. Ltd.
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Tanaka Hiroaki
Department Of Cardiovascular Medicine Tottori University Fuculty Of Medicine
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Wahdan Abdel-moneim
Faculty Of Engineering Ain Shams University
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SAKANUSHI Keishi
Department of Communications and Integrated Systems, Tokyo Institute of Technology
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Ota Yutaka
Center For Semiconductor Research And Development Toshiba Corporation Semiconductor Company
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HIEDA Takuji
Department of Information Systems Engineering, Graduate School of Information Science and Technology
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TAGAWA Hiroki
Center for Semiconductor Research and Development, Toshiba Corporation Semiconductor Company
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MATSUMOTO Nobu
Center for Semiconductor Research and Development, Toshiba Corporation Semiconductor Company
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Hieda Takuji
Department Of Information Systems Engineering Graduate School Of Information Science And Technology
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Tagawa Hiroki
Center For Semiconductor Research And Development Toshiba Corporation Semiconductor Company
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Matsumoto Nobu
Center For Semiconductor Research And Development Toshiba Corporation Semiconductor Company
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Takeuchi Yoshinori
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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Tanaka Hiroaki
Graduate School Of Engineering The University Of Tokyo
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Tanaka Hiroaki
Department Of Biology Aichi University Of Education
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Imai Masaharu
Department Of Informatics And Mathematical Science Graduate School Of Engineering Science Osaka Univ
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TANIGUCHI Ittetsu
Ritsumeikan University
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KOBAYASHI Ayataka
Osaka University
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Iwato Hirofumi
Osaka University
著作論文
- Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors
- Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems
- Reconfigurable AGU : An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors
- Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram(System Level Design,VLSI Design and CAD Algorithms)
- VLSI Architecture for Real-Time Fractal Image Coding Processors (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
- Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
- Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design
- A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions