Kajihara Seiji | Kyushu Inst. Technol. Iizuka‐shi Jpn

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概要

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著作論文

Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan(Special Issue on Test and Verification of VLSI)
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme
A Study of Capture-Safe Test Generation Flow for At-Speed Testing
Scan Tree Design: Test Compression with Test Vector Modification (特集:システムLSIの設計技術と設計自動化)
On Delay Test Quality for Test Cubes
A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
A Statistical Quality Model for Delay Testing (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing
Estimation of Delay Test Quality and Its Application to Test Generation
Delay Testing: Improving Test Quality and Avoiding Over-testing

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