Scan Tree Design: Test Compression with Test Vector Modification (特集:システムLSIの設計技術と設計自動化)

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概要

• 論文の詳細を見る

• This paper presents a method to reduce test data volume and test application time for a full-scan circuit. The proposed method constructs a scan tree in which scan flip-flops are placed and routed in a tree structure. Although one scan input to the scan tree drives several can chains with varying length, it is guaranteed that every test vector of a test set can be loaded into the scan tree. Since the height of the scan tree decides test data volume of the test set, the method modifies the test set so as to minimize the height. The procedure of test vector modification consists of don't care identification for the test set and a solution to a vertex coloring problem for an incompatibility graph constructed from the test set including don't cares. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce, on the average, test data volume and test application time by 70%.

• 2004-05-15

著者

• MIYASE Kohei

  Kyushu Institute of Technology

• Miyase K

  Kyushu Institute Of Technology

• Kajihara Seiji

  Kyushu Insteitute Of Technology

• Miyase Kohei

  Faculty Of Computer Science And Systems Engineering Kyushu Institute Of Technology

• Kajihara Seiji

  Kyushu Inst. Technol. Iizuka‐shi Jpn

関連論文

• High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme
• Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan(Special Issue on Test and Verification of VLSI)
• High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme
• A Study of Capture-Safe Test Generation Flow for At-Speed Testing
• On Detection of Bridge Defects with Stuck-at Tests
• A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits
• Scan Tree Design: Test Compression with Test Vector Modification (特集:システムLSIの設計技術と設計自動化)
• A Novel ATPG Method for Capture Power Reduction during Scan Testing(Dependable Computing)
• A Per-Test Fault Diagnosis Method Based on the X-Fault Model(Dependable Computing)
• Don't Care Identification and Statistical Encoding for Test Data Compression(Test Generation and Compaction)(Test and Verification of VLSI)
• On Delay Test Quality for Test Cubes
• A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing
• Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
• A Statistical Quality Model for Delay Testing (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
• A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing
• Estimation of Delay Test Quality and Its Application to Test Generation
• Delay Testing: Improving Test Quality and Avoiding Over-testing

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