A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing
スポンサーリンク
概要
- 論文の詳細を見る
Test power has become a critical issue, especially for low-power devices with deeply optimized functional power profiles. Particularly, excessive capture power in at-speed scan testing may cause timing failures that result in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. However, previous capture-safety checking metrics suffer from inadequate accuracy since they ignore the time relations among different transitions caused by a test vector in a circuit. This paper presents a novel metric called the Transition-Time-Relation-based (TTR) metric which takes transition time relations into consideration in capture-safety checking. Detailed analysis done on an industrial circuit has demonstrated the advantages of the TTR metric. Capture-safety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation.
著者
-
MIYASE Kohei
Kyushu Institute of Technology
-
WEN Xiaoqing
Kyushu Institute of Technology
-
Kajihara Seiji
Kyushu Inst. Technol. Iizuka‐shi Jpn
-
YAMATO Yuta
Fukuoka Industry Science Technology Foundation
-
SAKAI Ryota
Kyushu Institute of Technology
-
ASO Masao
Renesas Micro Systems Co. Ltd.
-
FURUKAWA Hiroshi
Renesas Micro Systems Co. Ltd.
関連論文
- High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme
- Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan(Special Issue on Test and Verification of VLSI)
- Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time(Dependable Computing)
- Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores(Dependable Computing)
- High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme
- A Study of Capture-Safe Test Generation Flow for At-Speed Testing
- On Detection of Bridge Defects with Stuck-at Tests
- A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits
- Scan Tree Design: Test Compression with Test Vector Modification (特集:システムLSIの設計技術と設計自動化)
- A Novel ATPG Method for Capture Power Reduction during Scan Testing(Dependable Computing)
- A Per-Test Fault Diagnosis Method Based on the X-Fault Model(Dependable Computing)
- A New Method for Low-Capture-Power Test Generation for Scan Testing(Dependable Computing)
- On Design for I_-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies(Computer Components)
- Testing Core-Based System-on-a-Chip Designs
- Transistor Leakage Fault Diagnosis for CMOS Circuits(Special Issue on Test and Diagnosis of VLSI)
- Transistor Leakage Fault Diagnosis with I_DDQ and Logic Information
- Testing of k-FR Circuits under Highly Observable Condition
- On Delay Test Quality for Test Cubes
- A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing
- Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
- A Statistical Quality Model for Delay Testing (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing
- Estimation of Delay Test Quality and Its Application to Test Generation
- Delay Testing: Improving Test Quality and Avoiding Over-testing