Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores(Dependable Computing)
スポンサーリンク
概要
- 論文の詳細を見る
Connection of internal scan chains in core wrapper design (CWD) is necessary to handle the width match of TAM and internal scan chains. However, conventional serial connection of internal scan chains incurs power and time penalty. Study shows that the distribution and high density of don't care bits (X-bits) in test patterns make scan slices overlapping and partial overlapping possible. A novel parallel CWD (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns. In order to achieve shift time reduction from overlapping in pCWD, a two-phase process on test pattern : partition and fill, is presented. Experimental results on d695 of ITC2002 benchmark demonstrated the shift time and test power have been decreased by 1.5 and 15 times, respectively. In addition, the proposed pCWD can be used as a stand-alone time reduction technique, which has better performance than previous techniques.
- 社団法人電子情報通信学会の論文
- 2005-09-01
著者
-
Han Yinhe
Institute Of Computing Technology Chinese Academy Of Sciences
-
Li Xiaowei
Institute Of Computing Technology Chinese Academy Of Sciences
-
WEN Xiaoqing
Kyushu Institute of Technology
-
HU Yu
Institute of Computing Technology, Chinese Academy of Sciences
-
LI Huawei
Institute of Computing Technology, Chinese Academy of Sciences
-
WEN Xiaoqing
Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology
-
CHANDRA Anshuman
Synopsys, Inc.
-
Hu Yu
Institute Of Computing Technology Chinese Academy Of Sciences
-
Li Huawei
Institute Of Computing Technology Chinese Academy Of Sciences
-
Wen Xiaoqing
Faculty Of Computer Science And Systems Engineering Kyushu Institute Of Technology
-
Hu Yu
Institute Of Biomedical Engineering Central South University
-
Xiaoqing Wen
Department Of Information Engineering Mining College Akita University
-
Chandra Anshuman
Synopsys Inc.
-
Han Yinhe
Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academy
-
Li Xiaowei
Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academy Of Sciences
関連論文
- High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme
- Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time(Dependable Computing)
- Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores(Dependable Computing)
- Lentiviral shRNA silencing of BDNF inhibits in vivo multiple myeloma growth and angiogenesis via down-regulated stroma-derived VEGF expression in the bone marrow milieu
- Successful treatment of myeloid neoplasms associated with PDGFRA rearrangement with imatinib mesylate
- Labeling Polymeric Nanoparticles with Copper Chlorophyll as Contrast Agent for Electron Microscopy
- BAT : Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission
- High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme
- A Study of Capture-Safe Test Generation Flow for At-Speed Testing
- On Detection of Bridge Defects with Stuck-at Tests
- A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits
- A Novel ATPG Method for Capture Power Reduction during Scan Testing(Dependable Computing)
- A Per-Test Fault Diagnosis Method Based on the X-Fault Model(Dependable Computing)
- A New Method for Low-Capture-Power Test Generation for Scan Testing(Dependable Computing)
- On Design for I_-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies(Computer Components)
- Testing Core-Based System-on-a-Chip Designs
- Transistor Leakage Fault Diagnosis for CMOS Circuits(Special Issue on Test and Diagnosis of VLSI)
- Transistor Leakage Fault Diagnosis with I_DDQ and Logic Information
- Testing of k-FR Circuits under Highly Observable Condition
- Overexpression of EphA2, MMP-9 and MVD-CD34 in hepatocellular carcinoma : Implications for tumor progression and prognosis
- On Delay Test Quality for Test Cubes
- A New Multiple-Round Dimension-Order Routing for Networks-on-Chip
- A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing
- Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
- A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing
- Estimation of Delay Test Quality and Its Application to Test Generation