Li Xiaowei | Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academy Of Sciences

スポンサーリンク

概要

• LI Xiaoweiの詳細を見る
• 同名の論文著者
• Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academy Of Sciencesの論文著者

関連著者

• Li Huawei

  Institute Of Computing Technology Chinese Academy Of Sciences

• Han Yinhe

  Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academy

• Li Xiaowei

  Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academy Of Sciences

• Han Yinhe

  Institute Of Computing Technology Chinese Academy Of Sciences

• Li Xiaowei

  Institute Of Computing Technology Chinese Academy Of Sciences

• WEN Xiaoqing

  Kyushu Institute of Technology

• HU Yu

  Institute of Computing Technology, Chinese Academy of Sciences

• LI Huawei

  Institute of Computing Technology, Chinese Academy of Sciences

• WEN Xiaoqing

  Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology

• Hu Yu

  Institute Of Computing Technology Chinese Academy Of Sciences

• Wen Xiaoqing

  Faculty Of Computer Science And Systems Engineering Kyushu Institute Of Technology

• Hu Yu

  Institute Of Biomedical Engineering Central South University

• Xiaoqing Wen

  Department Of Information Engineering Mining College Akita University

• CHANDRA Anshuman

  Synopsys, Inc.

• Li Xiaowei

  Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academi

• Han Yinhe

  Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academy

• Li Huawei

  Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academi

• Chandra Anshuman

  Synopsys Inc.

• Fu Binzhang

  Key Laboratory Of Computer System And Architecture Institute Of Computing Technology Chinese Academy

もっと見る 閉じる

著作論文

• Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time(Dependable Computing)
• Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores(Dependable Computing)
• A New Multiple-Round Dimension-Order Routing for Networks-on-Chip

スポンサーリンク