High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

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概要

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• At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of dont care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.

著者

• MIYASE Kohei

  Kyushu Institute of Technology

• WEN Xiaoqing

  Kyushu Institute of Technology

• FURUKAWA Hiroshi

  Kyushu Institute of Technology

• YAMATO Yuta

  Kyushu Institute of Technology

• KAJIHARA Seiji

  Kyushu Institute of Technology

• GIRARD Patrick

  LIRMM

• WANG Laung-Terng

  SynTest

• TEHRANIPOOR Mohammad

  University of Connecticut

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