A Statistical Quality Model for Delay Testing (Signal Integrity and Variability, <Special Section> VLSI Design Technology in the Sub-100nm Era)
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概要
- 論文の詳細を見る
In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.
- 一般社団法人電子情報通信学会の論文
著者
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KAJIHARA Seiji
Kyushu Institute of Technology
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Hamada Shuji
Semiconductor Technology Academic Research Center
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Kajihara Seiji
Kyushu Insteitute Of Technology
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SATO Yasuo
Semiconductor Technology Academic Research Center (STARC)
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Takatori Atsuo
Semiconductor Technology Academic Research Center
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MAEDA Toshiyuki
Semiconductor Technology Academic Research Center
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Sato Yasuo
Semiconductor Technology Academic Research Center
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Kajihara Seiji
Kyushu Inst. Technol. Iizuka‐shi Jpn
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- On Delay Test Quality for Test Cubes
- A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing
- Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
- A Statistical Quality Model for Delay Testing (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing
- Estimation of Delay Test Quality and Its Application to Test Generation
- Delay Testing: Improving Test Quality and Avoiding Over-testing