Don't Care Identification and Statistical Encoding for Test Data Compression(Test Generation and Compaction)(<Special Section>Test and Verification of VLSI)

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概要

• 論文の詳細を見る

• This paper describes a method of test data compression for a given test set using statistical encoding. In order to maximize the effectiveness of statistical encoding, the method first converts some specified input values in the test set to unspecified ones without losing fault coverage, and then reassigns appropriate logic values to the unspecified inputs. Experimental results for ISCAS-89 benchmark circuits show that the proposed method can on the average reduce the test data volume to less than 25% of that required for the original test set.

• 社団法人電子情報通信学会の論文
• 2004-03-01

著者

• Reddy S

  Univ. Iowa Usa

• KAJIHARA Seiji

  Department of Computer Science and Electronics of Kyushu Institute of Technology

• Miyase K

  Kyushu Institute Of Technology

• Miyase Kohei

  Department Of Computer Sciences And Electronics Kyushu Institute Of Technology

• POMERANZ Irith

  School of Electrical and Computer Engineering, Purdue University

• Miyase Kohei

  Faculty Of Computer Science And Systems Engineering Kyushu Institute Of Technology

• Pomeranz Irith

  School Of Electrical And Computer Engineering Purdue University

• TANIGUCHI Kenjiro

  Department of Computer Sciences and Electronics, Kyushu Institute of Technology

• REDDY Sudhakar

  Electrical and Computer Engineering Department, University of Iowa

• Taniguchi Kenjiro

  Department Of Computer Sciences And Electronics Kyushu Institute Of Technology

関連論文

• FOREWORD
• High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX : A Clock-Gating-Based Test Relaxation and X-Filling Scheme
• On Finding Don't Cares in Test Sequences for Sequential Circuits(Dependable Computing)
• A Method of Static Test Compaction Based on Don't Care Identification (特集:システムLSIの設計技術と設計自動化)
• A Study of Capture-Safe Test Generation Flow for At-Speed Testing
• On Detection of Bridge Defects with Stuck-at Tests
• A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits
• Scan Tree Design: Test Compression with Test Vector Modification (特集:システムLSIの設計技術と設計自動化)
• A Novel ATPG Method for Capture Power Reduction during Scan Testing(Dependable Computing)
• A Per-Test Fault Diagnosis Method Based on the X-Fault Model(Dependable Computing)
• Don't Care Identification and Statistical Encoding for Test Data Compression(Test Generation and Compaction)(Test and Verification of VLSI)
• On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis(Dependable Computing)
• A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing
• Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
• Scan-Out Power Reduction for Logic BIST

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