A 24dB Gain 51-68GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors
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概要
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At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6dB MAG improvement is realized when Dgd changes from 60nm to 200nm. A four-stage common-source low noise amplifier is implemented in a 65nm CMOS process. A measured peak power gain of 24dB is achieved with a power dissipation of 30mW from a 1.2-V power supply. An 18dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17GHz from 51GHz to 68GHz, and noise figure (NF) is from 4.0dB to 7.6dB.
著者
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Bunsen Keigo
Department Of Physical Electronics Tokyo Institute Of Technology
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Li Ning
Department Of Analytical Chemistry Shenyang Pharmaceutical University
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Okada Kenichi
Department Of Communications And Computer Engineering Kyoto University
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Matsuzawa Akira
Department Of Physical Electronics Graduate School Of Science And Engineering Tokyo Institute Of Technology
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Kawano Yoichi
Advanced Devices Lab. Fujitsu Laboratories Ltd.
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SUZUKI Toshihide
Advanced Devices Lab., Fujitsu Laboratories Ltd.
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SATO Masaru
Advanced Devices Lab., Fujitsu Laboratories Ltd.
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HIROSE Tatsuya
Advanced Devices Lab., Fujitsu Laboratories Ltd.
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Takayama Naoki
Department Of Physical Electronics Graduate School Of Science And Engineering Tokyo Institute Of Technology
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Bu Qinghong
Department Of Physical Electronics Graduate School Of Science And Engineering Tokyo Institute Of Technology
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Kawano Yoichi
Advanced Devices Lab., Fujitsu Laboratories Ltd.
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Matsuzawa Akira
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology
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TAKAYAMA Naoki
Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology
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