The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time(<Special Section>Analog Circuits and Related SoC Integration Technologies)
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概要
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In this paper, we discuss the effects of switch resistances on the step response of switched-capacitor (SC) circuits, especially multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters. Theory and simulation results reveal that the settling time of MDACs can be decreased by optimizing the switch resistances. This switch resistance optimization does not only effectively increase the speed of single-bit MDACs, but also of multi-bit MDACs. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. With such an optimization, the response of the switch will be improved by up to 50%.
- 2007-06-01
著者
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MIYAHARA Masaya
Department of Physical Electronics, Tokyo Institute of Technology
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MATSUZAWA Akira
Department of Physical Electronics, Tokyo Institute of Technology
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Matsuzawa Akira
Department Of Physical Electronics Tokyo Institute Of Technology
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Matsuzawa Akira
Tokyo Inst. Of Technol. Tokyo Jpn
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Miyahara Masaya
Tokyo Inst. Of Technol. Tokyo Jpn
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Miyahara Masaya
Department Of Physical Electronics Tokyo Institute Of Technology
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Matsuzawa Akira
Department Of Physical Electronics Graduate School Of Science And Engineering Tokyo Institute Of Technology
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