Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs
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概要
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This paper describes the analysis and design of low-noise analog circuits for a new architecture readout LSI, Qpix. In contrast to conventional readout LSIs using TOT method, Qpix measures deposited charge directly as well as time information. A preamplifier with a two-stage op amp and current-copy output buffers is proposed to realize these functions. This preamplifier is configured to implement a charge sensitive amplifier (CSA) and a trans-impedance amplifier (TIA). Design issues related to CSA are analyzed, which includes gain requirement of the op amp, stability and compensation of the two-stage cascode op amp, noise performance estimation, requirement for the resolution of the ADC and time response. The offset calibration method in the TIA to improve the charge detecting sensitivity is also presented. Also, some design principles for these analog circuits are presented. In order to verify the theoretical analysis, a 400-pixel high speed readout LSI: Qpix v.1 has been designed and fabricated in 180nm CMOS process. Calculations and SPICE simulations show that the total output noise is about 0.31mV (rms) at the output of the CSA and the offset voltage is less than 4mV at the output of the TIA. These are attractive performances for experimental particle detector using Qpix v.1 chip as its readout LSI.
著者
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Li Fei
Department of Pharmacology, Zunyi Medical College
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Miyahara Masaya
Department Of Physical Electronics Tokyo Institute Of Technology
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Matsuzawa Akira
Department Of Physical Electronics Graduate School Of Science And Engineering Tokyo Institute Of Technology
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