A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells
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概要
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In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4bit SA-TDCs with short latency. The chip operates up to 4.4GHz. The measured ENOB is 3.51bit and FOM is 0.49pJ/conv.
著者
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Dosho Shiro
Strategic Semiconductor Development Center Matsushita Electric Industrial Co. Ltd.
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Miyahara Masaya
Department Of Physical Electronics Tokyo Institute Of Technology
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Matsuzawa Akira
Department Of Physical Electronics Graduate School Of Science And Engineering Tokyo Institute Of Technology
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TAKAYAMA Masao
Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd.
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TAKEDA Noriaki
Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd.
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