A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs (Special Issue on Synthesis and Verification of Hardware Design)

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概要

• 論文の詳細を見る

• As IC fabrication technology enters a deep-submicron region with device feature sizes lt0.35μm, interconnect becomes the most dominant factor in design of high-speed Application Specific Integrated Circuits (ASICs). This paper proposes a novel methodology for automated data-path synthesis of such circuits and outlines algorithms to support it. In contrast to other approaches, we formulate interconnect area/delay optimizations as high-level synthesis transformations and use them during the synthesis to minimize the impact of wiring on circuit characteristics. Experiments with FIR filter implementations show that such formulation jointly with "on the fly" module generation and performance-driven floorplanning provides more than a 30% reduction in wiring delay for deep sub-micron designs.

• 社団法人電子情報通信学会の論文
• 1996-10-25

著者

• TAMARU Keikichi

  Department of Electronics and Communication, Graduate School of Engineering, Kyoto University

• Tamaru Keikichi

  Department Of Communications And Computer Engineering Kyoto University

• Moshnyaga Vasily

  Department of Electronics, Kyoto University

• Moshnyaga Vasily

  Department Of Electronics Kyoto University

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