Omitting Cache Look-up for High-Performance, Low-Power Microprocessors(<特集>Special Issue on High-Performance and Low-Power Microprocessors)

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概要

• 論文の詳細を見る

• In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "historybased tag-comparison (HBTC) cache." The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.

• 社団法人電子情報通信学会の論文
• 2002-02-01

著者

• Inoue Koji

  Department of Cardiology, St.Mariannna University School of Medicine

• Murakami Kazuaki

  Department Of Electronics Engineering And Computer Science Fukuoka University

• Murakami Kazuaki

  The Authors Are With The Department Of Computer Science And Communication Engineering Kyushu Univers

• Murakami K

  Department Of Informatics Kyushu University

• モシニャガ ワシリー

  Department Of Informatics Kyushu University

• Moshnyaga Vasily

  Department of Electronics, Kyoto University

• Murakami Kazuaki

  Department Of Computer Science And Communication Engineering Kyushu University

• Moshnyaga Vasily

  京都大学工学研究科電子通信工学教室

• Moshnyaga Vasily

  Department Of Electronics Kyoto University

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