Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
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概要
- 論文の詳細を見る
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for high-performance microprocessor designs. Since on-chip caches are major contributors of the leakage, a number of researchers have proposed efficient leakage reduction techniques. However, it is still not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer these questions, we explore runtime cache management algorithm, and evaluate the energy-performance efficiency for several alternatives.
- 2005-04-01
著者
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Inoue Koji
Department of Cardiology, St.Mariannna University School of Medicine
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Murakami Kazuaki
Department Of Electronics Engineering And Computer Science Fukuoka University
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Murakami Kazuaki
The Authors Are With The Department Of Computer Science And Communication Engineering Kyushu Univers
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Murakami K
Department Of Informatics Kyushu University
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モシニャガ ワシリー
Department Of Informatics Kyushu University
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Moshnyaga Vasily
Department of Electronics, Kyoto University
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INOUE Koji
Kyushu University
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KOMIYA Reiko
Department of Electronics Engineering and Computer Science, Fukuoka University
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Komiya Reiko
Department Of Electronics Engineering And Computer Science Fukuoka University:institute Of Systems &
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Murakami Kazuaki
Department Of Computer Science And Communication Engineering Kyushu University
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Moshnyaga Vasily
京都大学工学研究科電子通信工学教室
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Moshnyaga Vasily
Department Of Electronics Kyoto University
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MURAKAMI Kazuaki
Institute of Systems & Information Technologies/KYUSHU
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