Register-Transfer Module Selection for Sub-Micron ASIC Design : LETTER Special Issue on Synthesis and Verification of Hardware Design
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概要
- 論文の詳細を見る
In order to shorten the time-to-market, Application-Specific Integrated Circuits (ASIC's) are designed from a library of pre-defined layout implementations for register-transfer modules such as multipliers, adders, RAM, ROM, etc. Current approaches to selecting the implementations from the library usually deal with their timing-area estimates and do not consider delay of the intermodule wiring. However, as sub-micron design rules are utilized for IC fabrication, wiring delay becomes comparable to the functional unit delay and can not longer be ignored even in register-transfer synthesis. In this paper we propose an algorithm that combines module selection with Performance-Driven module placement and reduces an impact of wiring on sub-micron ASIC performance. The algorithm not only efficiently exploits multiple module realizations in the design library, but also finds the module placement which minimizes wiring delay. Experimental results on several benchmarks show that considering both module and wiring issues, more than 30% reduction of the total circuit delay can be achieved.
- 社団法人電子情報通信学会の論文
- 1995-03-25
著者
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MORI Yutaka
Department of Radiology, Jikei University School of Medicine
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Mori Yutaka
Department Of Internal Medicine National Hospital Organization Utsunomiya National Hospital
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TAMARU Keikichi
Department of Electronics and Communication, Graduate School of Engineering, Kyoto University
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Tamaru Keikichi
Department Of Electronics Kyoto University
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Tamaru Keikichi
Department Of Communications And Computer Engineering Kyoto University
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Moshnyaga Vasily
Department of Electronics, Kyoto University
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Mori Yutaka
Department Of Chemistry
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Moshnyaga Vasily
Department Of Electronics Kyoto University
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Mori Yutaka
Department Of Electronics Kyoto University
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Mori Yutaka
Department Of Applied Chemistry Graduate School Of Engineering Osaka City University
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