Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_<TH>/V_<DD> and Micro-V_<DD>-Hopping (Low Power Techniques, <Special Section> VLSI Design Technology in the Sub-100nm Era)
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概要
- 論文の詳細を見る
A low-power FPGA design approach is proposed based on a fine-grain V_<DD> control scheme called micro-V_<DD>-hopping. Four configurable logic blocks (CLBs) are grouped into one block where V_<DD> is shared. In the micro-V_<DD>-hopping scheme, V_<DD> in each block is changed between V_<DDH> (high V_<DD>) and V_<DDL> (low V_<DD>) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for lowswing inter-block signals. The FPGA incorporates the Zigzag power-gating scheme, in which special care has been taken to cope with a sneak leakagepath problem. A test chip was fabricated using a 0.35-μm CMOS technology, together with the conventional fixed-V_<DD> FPGA for comparison. Measurement results show that dynamic power in the proposed scheme can be reduced by 86% when a frequency is half of the maximum one. Simulation using a 90-nm CMOS technology shows that leakage power can be reduced by 97%, when the proposed method is used. The area overhead of the proposed FPGA is 2%.
- 社団法人電子情報通信学会の論文
著者
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Tran Canh
The University Of Tokyo
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SAKURAI Takayasu
The University of Tokyo
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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Kawaguchi Hiroshi
Kobe University
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