A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network
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概要
- 論文の詳細を見る
A 315MHz power-gated ultra low power transceiver for wireless sensor network is developed in 40nm CMOS. The developed transceiver features an injection-locked frequency multiplier for carrier generation and a power-gated low noise amplifier with current second-reuse technique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby achieves 11µW power consumption at 315MHz. The proposed low noise amplifier achieves the lowest power consumption of 8.4µW with 7.9dB noise figure and 20.5dB gain in state-of-the-art designs.
著者
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TAKAMIYA Makoto
The University of Tokyo
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SAKURAI Takayasu
The University of Tokyo
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Takamiya Makoto
The Univ. Of Tokyo
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LIU Lechang
The University of Tokyo
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- A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network
- A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network