A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57% ripple reduction (集積回路)

スポンサーリンク

概要

• 論文の詳細を見る

• To effectively reduce output ripple of switched-capacitor DC-DC converters which generate variable output voltages, a novel feedback control scheme is presented. The proposed scheme uses pulse density and width modulation (PDWM) to reduce the output ripple with low output voltage. The prototype chip was implemented using 65nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional pulse density modulation (PDM), the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.

• 2010-12-09

著者

• ISHIDA Koichi

  The University of Tokyo

• TAKAMIYA Makoto

  The University of Tokyo

• SAKURAI Takayasu

  The University of Tokyo

• Takamiya Makoto

  Institute Of Industrial Science The University Of Tokyo

• Sakurai Takayasu

  Institute Of Industrial Science The University Of Tokyo

• Chen Po-hung

  The University Of Tokyo

• Okuma Yasuyuki

  Semiconductor Technology Academic Research Center (starc)

• Zhang Xin

  The University Of Tokyo

• Pu Yu

  University of Tokyo

• Ryu Yoshikatsu

  Semiconductor Technology Academic Research Center (STARC)

• PU Yu

  The University of Tokyo

• CHEW Po-Hong

  The University of Tokyo

• WATANABE Kazunori

  Semiconductor Technology Academic Research Center (STARC)

• Takamiya Makoto

  The Univ. Of Tokyo

関連論文

• Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
• Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits
• Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
• High Performance Accumulated Back-Interface Dynamic Threshold SOI MOS-FET's (AB-DTMOS) with Large Body Effect at Low Supply Voltage
• A 100Mbps, 4.1pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90nm CMOS
• An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
• A 20% Power Reduction in Two-stage Opamp by Source-Degenerated Active-Load Phase Compensation
• Optimum Condutions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs
• Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs
• Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
• A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)
• Measurement of Energetic and Lateral Distribution of Interface State Density in Fully-Depleted Silicon on Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
• High-Performance Accumulated Back-Interface Dynamic Threshold SOI MOSFET (AB-DTMOS) with Large Body Effect at Low Supply Voltage
• Measurement of Energetic and Lateral Distribution of Interface State Density in FD SOI MOSFETs
• Suppression of Geometric Component of Charge Pumping Current in Thin Film Silicon on Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
• New Measurement Technique for Sub-Bandgap Impact Ionization Current by Transient Characteristics of Partially Depleted SOI MOSFETs
• Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
• A 1.76mW, 100Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS
• Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_/V_ and Micro-V_-Hopping (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
• Trends of On-Chip Interconnects in Deep Sub-Micron VLSI (Interconnect Technique, VLSI Design Technology in the Sub-100nm Era)
• C-12-58 0.18-V Input Charge Pump with Forward Body Biasing
• Misleading energy and performance claims in sub/near threshold digital systems (集積回路)
• A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57% ripple reduction (集積回路)
• A charge-domain auto- and cross-correlation based IR-UWB receiver with power- and area-efficient PLL for 62.5ps step data synchronization in 65nm CMOS (集積回路)
• A-3-7 Inductance Effect on VLSI Interconnections
• An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise
• 0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications
• 0.6V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver
• 0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS
• 1Gb/s, 50μm×50μm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling
• A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage
• Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout
• 0.45-V Input Higher Than 90% Efficiency Buck Converter with On-Chip Gate Boost (シリコン材料・デバイス)
• 0.45-V Input Higher Than 90% Efficiency Buck Converter with On-Chip Gate Boost (集積回路)
• A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network
• A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network
• Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)
• 0.45-V Input Higher Than 90% Efficiency Buck Converter with On-Chip Gate Boost
• 0.45-V Input Higher Than 90% Efficiency Buck Converter with On-Chip Gate Boost
• Measurement of Energetic and Lateral Distribution of Interface State Density in Fully-Depleted Silicon on Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
• 0.45-V Input Higher Than 90% Efficiency Buck Converter with On-Chip Gate Boost
• 0.45-V Input Higher Than 90% Efficiency Buck Converter with On-Chip Gate Boost

もっと見る 閉じる

スポンサーリンク