Misleading energy and performance claims in sub/near threshold digital systems (集積回路)

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概要

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• Many of us in the field of ultra-low-V_<dd> processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates three major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower V_<dd> with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different V_<th> definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's V_<dd> and energy could scale as well as standard cells. Therefore, the actual energy benefit from using a sub/near threshold V_<dd> can be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-V_<dd> systems. The outlined pitfalls also shed light on future directions in this field.

• 2010-12-09

著者

• TAKAMIYA Makoto

  The University of Tokyo

• Takamiya Makoto

  Institute Of Industrial Science The University Of Tokyo

• Takamiya Makoto

  University Of Tokyo

• Sakurai Takayasu

  University Of Tokyo

• Sakurai Takayasu

  Institute Of Industrial Science The University Of Tokyo

• Zhang Xin

  The University Of Tokyo

• Takata Hidehiro

  Semiconductor Technology Academic Research Center

• Pu Yu

  University of Tokyo

• Zhang Xin

  University of Tokyo

• Huang Jim

  University of Tokyo

• Muramatsu Atsushi

  Semiconductor Technology Academic Research Center

• Nomura Masahiro

  Semiconductor Technology Academic Research Center

• Hirairi Koji

  Semiconductor Technology Academic Research Center

• Sakurabayashi Taro

  Semiconductor Technology Academic Research Center

• Miyano Shinji

  Semiconductor Technology Academic Research Center

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