Sakurai Takayasu | Institute Of Industrial Science The University Of Tokyo

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著作論文

Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
A 100Mbps, 4.1pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90nm CMOS
An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
A 20% Power Reduction in Two-stage Opamp by Source-Degenerated Active-Load Phase Compensation
A 1.76mW, 100Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS
C-12-58 0.18-V Input Charge Pump with Forward Body Biasing
Misleading energy and performance claims in sub/near threshold digital systems (集積回路)
A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57% ripple reduction (集積回路)
A charge-domain auto- and cross-correlation based IR-UWB receiver with power- and area-efficient PLL for 62.5ps step data synchronization in 65nm CMOS (集積回路)
A-3-7 Inductance Effect on VLSI Interconnections
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise
0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications
0.6V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS
A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage
Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout

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