SAKURAI Takayasu | The University of Tokyo

スポンサーリンク

概要

関連著者

もっと見る

著作論文

Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)
Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_/V_ and Micro-V_-Hopping (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
Trends of On-Chip Interconnects in Deep Sub-Micron VLSI (Interconnect Technique, VLSI Design Technology in the Sub-100nm Era)
C-12-58 0.18-V Input Charge Pump with Forward Body Biasing
A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57% ripple reduction (集積回路)
1Gb/s, 50μm×50μm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling
A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage
Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout
A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network
A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network

もっと見る

スポンサーリンク