ISHIDA Koichi | The University of Tokyo

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著作論文

Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
A 100Mbps, 4.1pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90nm CMOS
An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
A 20% Power Reduction in Two-stage Opamp by Source-Degenerated Active-Load Phase Compensation
C-12-58 0.18-V Input Charge Pump with Forward Body Biasing
A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57% ripple reduction (集積回路)
0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS
A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage

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