An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors(Analog and Communications,<Special Section>Low-Power, High-Speed LSIs and Related Technologies)
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概要
- 論文の詳細を見る
An opamp design with outside-rail output relaxing a low-voltage constraint on future scaled transistors is presented. The proposed opamp realizes 3-V output swing without gate-oxide stress although implemented in a 1.8-V 0.18-μm standard CMOS process. The 3-V-output operation is experimentally verified. The outside-rail output design with scaled transistors shows area advantage over un-scaled and inside-rail design while keeping signal-to-noise ratio and gain bandwidth constant. The chip area is estimated to be 47% of the conventional opamp using a 0.35-μm CMOS and about an order of magnitude smaller compared with the conventional inside-rail 0.18-μm CMOS design due to reduced capacitor area. The proposed design could be extended to n-tuple V_<DD> operation and applied to circuits with a feed back loop such as gain stage and filters. The extendibility of n-tuple V_<DD> operation and its application are discussed with simulation results.
- 社団法人電子情報通信学会の論文
- 2007-04-01
著者
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TAKAMIYA Makoto
VLSI Design and Education Center, The University of Tokyo
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SAKURAI Takayasu
Center for Collaborative Research,the University of Tokyo
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ISHIDA Koichi
The University of Tokyo
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TAKAMIYA Makoto
The University of Tokyo
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ISHIDA Koichi
Center for Collaborative Research, The University of Tokyo
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TAMTRAKARN Atit
Center for Collaborative Research, The University of Tokyo
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ISHIKURO Hiroki
Department of Electronics and Electrical Engineering, Keio University
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Ishikuro Hiroki
Keio Univ. Yokohama‐shi Jpn
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Takamiya Makoto
Institute Of Industrial Science The University Of Tokyo
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Sakurai Takayasu
Institute Of Industrial Science The University Of Tokyo
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Ishikuro Hiroki
Department Of Electronics And Electrical Engineering Keio University
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Sakurai Takayasu
Center For Collaborative Research And Institute Of Industrial Science The University Of Tokyo
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Tamtrakarn Atit
Center For Collaborative Research The University Of Tokyo:(present Office)sony Corporation
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