A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme

スポンサーリンク

概要

• 論文の詳細を見る
• 2010-01-01

著者

• KURODA Tadahiro

  Keio University, Dept. of Electronics and Electrical Engineering

• Kuroda Tadahiro

  Keio Univ.

• ISHIKURO Hiroki

  Keio University

• KULKARNI Vishal

  Keio University

• Ishikuro Hiroki

  Keio Univ. Yokohama‐shi Jpn

関連論文

• A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter(Low-Power System LSI, IP and Related Technologies)
• Human activity recognition from environmental background sounds for wireless sensor networks (特集 知識情報化社会を支えるシステム技術)
• Non-contact 10% efficient 36mW power delivery using on-chip inductor in 0.18-μm CMOS (電子部品・材料)
• Chip-to-Chip Power Delivery by Inductive Coupling with Ripple Canceling Scheme
• Human activity recognition from environmental background sounds for wireless sensor networks (特集 知識情報化社会を支えるシステム技術)
• Digital Rosetta Stone : A Sealed Permanent Memory with Inductive-Coupling Power and Data Link
• A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65nm CMOS
• Measurement of Inductive Coupling in Wireless Superconnect
• An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
• Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC
• 18-GHz Clock Distribution Using a Coupled VCO Array(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
• Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link
• Constant Magnetic Field Scaling in Inductive-Coupling Data Link
• Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
• Constant Magnetic Field Scaling in Inductive-Coupling Data Link
• 60% Power Reduction in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique
• A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)
• System LSI : Challenges and Opportunities (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
• A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme
• Special Section on Low-Power, High-Speed LSIs and Related Technologies
• A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters(Analog, Low-Power LSI and Low-Power IP)
• A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65nm CMOS
• A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology
• A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range
• A 9-bit 100MS/s SAR ADC with Digitally Assisted Background Calibration
• Human action recognition using wireless wearable in-ear microphone (特集 医療・ヘルスケアにおける工学技術の新展開)
• High-Frequency Precise Characterization of Intrinsic FinFET Channel
• High-Frequency Precise Characterization of Intrinsic FinFET Channel
• A 9-bit 100MS/s SAR ADC with Digitally Assisted Background Calibration
• Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications
• A 4-10bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS with Wide Supply Voltage Range SAR Controller
• An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40nm CMOS
• Symbol-Rate Clock Recovery for Integrating DFE Receivers

もっと見る 閉じる

スポンサーリンク