Symbol-Rate Clock Recovery for Integrating DFE Receivers
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10Gb/s operation was also confirmed in the simulation with an 11dB channel loss at 5GHz.
著者
関連論文
- Non-contact 10% efficient 36mW power delivery using on-chip inductor in 0.18-μm CMOS (電子部品・材料)
- Chip-to-Chip Power Delivery by Inductive Coupling with Ripple Canceling Scheme
- Human activity recognition from environmental background sounds for wireless sensor networks (特集 知識情報化社会を支えるシステム技術)
- Digital Rosetta Stone : A Sealed Permanent Memory with Inductive-Coupling Power and Data Link
- Measurement of Inductive Coupling in Wireless Superconnect
- Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC
- 18-GHz Clock Distribution Using a Coupled VCO Array(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link
- Constant Magnetic Field Scaling in Inductive-Coupling Data Link
- Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- Constant Magnetic Field Scaling in Inductive-Coupling Data Link
- 60% Power Reduction in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique
- A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)
- System LSI : Challenges and Opportunities (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
- A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme
- Special Section on Low-Power, High-Speed LSIs and Related Technologies
- A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65nm CMOS
- A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology
- A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range
- A 9-bit 100MS/s SAR ADC with Digitally Assisted Background Calibration
- Human action recognition using wireless wearable in-ear microphone (特集 医療・ヘルスケアにおける工学技術の新展開)
- A 9-bit 100MS/s SAR ADC with Digitally Assisted Background Calibration
- Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications
- A 4-10bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS with Wide Supply Voltage Range SAR Controller
- An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40nm CMOS
- Symbol-Rate Clock Recovery for Integrating DFE Receivers