A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology (Interface and Interconnect Techniques, <Special Section> VLSI Design Technology in the Sub-100nm Era)

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概要

• 論文の詳細を見る

• A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35μm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2Gb/s/ch with 46mW power dissipation at 3.3V over 300μm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13μm in 70nm CMOS, 34Tbps/mm^2 will be obtained.

• 社団法人電子情報通信学会の論文

著者

• Kuroda Tadahiro

  Department of Electrical and Electronic Engineering Keio University

• KURODA Tadahiro

  Keio University, Dept. of Electronics and Electrical Engineering

• MIURA Noriyuki

  Keio University

• SAKURAI Takayasu

  The University of Tokyo

• MIZOGUCHI Daisuke

  Keio University, Department of Electronics and Electrical Engineering

• Miura Noriyuki

  Keio Univ.

• Kuroda Tadahiro

  Keio Univ.

• Miura Noriyuki

  Keio University Department Of Electronics And Electrical Engineering

• Mizoguchi Daisuke

  Keio University

• MIURA Noriyuki

  the Department of Electronics and Electrical Engineering, Keio University

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