Constant Magnetic Field Scaling in Inductive-Coupling Data Link
スポンサーリンク
概要
- 論文の詳細を見る
A wireless transceiver utilizing inductive coupling has been proposed for communication between chips in system in a package. This transceiver can achieve high-speed communication by using two-dimensional channel arrays. To increase the total bandwidth in the channel arrays, the density of the transceiver should be improved, which means that the inductor size should be scaled down. This paper discusses the scaling theory based on a constant magnetic field rule. By decreasing the chip thickness with the process scaling of 1/α, the inductor size can be scaled to 1/α and the data rate can be increased by α. As a result, the number of aggregated channels can be increased by α2 and the aggregated data band-width can be increased by α3. The scaling theory is verified by simulations and experiments in 350, 250, 180, and 90nm CMOS.
- （社）電子情報通信学会の論文
- 2008-02-01
著者
-
Kuroda Tadahiro
Department of Electrical and Electronic Engineering Keio University
-
KURODA Tadahiro
Keio University, Dept. of Electronics and Electrical Engineering
-
MIURA Noriyuki
Keio University
-
MIZOGUCHI Daisuke
Keio University, Department of Electronics and Electrical Engineering
-
Miura Noriyuki
Keio Univ.
-
Kuroda Tadahiro
Keio Univ.
-
ISHIKURO Hiroki
Keio University
-
Ishikuro Hiroki
Keio Univ. Yokohama‐shi Jpn
-
Ishikuro Hiroki
Soc Research And Development Center Toshiba Corporation
-
Miura Noriyuki
Keio University Department Of Electronics And Electrical Engineering
-
Mizoguchi Daisuke
Keio University
-
MIURA Noriyuki
the Department of Electronics and Electrical Engineering, Keio University
関連論文
- A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter(Low-Power System LSI, IP and Related Technologies)
- Human activity recognition from environmental background sounds for wireless sensor networks (特集 知識情報化社会を支えるシステム技術)
- Non-contact 10% efficient 36mW power delivery using on-chip inductor in 0.18-μm CMOS (電子部品・材料)
- Chip-to-Chip Power Delivery by Inductive Coupling with Ripple Canceling Scheme
- Non-contact 10% efficient 36mW power delivery using on-chip inductor in 0.18-μm CMOS (集積回路)
- Human activity recognition from environmental background sounds for wireless sensor networks (特集 知識情報化社会を支えるシステム技術)
- Digital Rosetta Stone : A Sealed Permanent Memory with Inductive-Coupling Power and Data Link
- A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65nm CMOS
- Measurement of Inductive Coupling in Wireless Superconnect (Special Issue: Solid State Devices & Materials)
- Measurement of Inductive Coupling in Wireless Superconnect
- An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC
- 18-GHz Clock Distribution Using a Coupled VCO Array(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link
- Constant Magnetic Field Scaling in Inductive-Coupling Data Link
- Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- Constant Magnetic Field Scaling in Inductive-Coupling Data Link
- 60% Power Reduction in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique
- A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)
- System LSI : Challenges and Opportunities (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
- Capacitor-Shunted Transmitter for Power Reduction in Inductive-Coupling Clock Link
- A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme
- Special Section on Low-Power, High-Speed LSIs and Related Technologies
- 60% power reduction in inductive-coupling inter-chip link by current-sensing technique (Special issue: Solid state devices and materials)
- A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters(Analog, Low-Power LSI and Low-Power IP)
- A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65nm CMOS
- A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology
- Capacitor-Shunted Transmitter for Power Reduction in Inductive-Coupling Clock Link
- A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range
- A 33% Improvement in Efficiency of Wireless Inter-Chip Power Delivery by Thin Film Magnetic Material for Three-Dimensional System Integration
- A 9-bit 100MS/s SAR ADC with Digitally Assisted Background Calibration
- 6W/25mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing
- Human action recognition using wireless wearable in-ear microphone (特集 医療・ヘルスケアにおける工学技術の新展開)
- High-Frequency Precise Characterization of Intrinsic FinFET Channel
- High-Frequency Precise Characterization of Intrinsic FinFET Channel
- 6W/25mm^2 Wireless Power Transmission for Non-contact Wafer-Level Testing
- A 9-bit 100MS/s SAR ADC with Digitally Assisted Background Calibration
- Measurement of Inductive Coupling in Wireless Superconnect
- Chip-to-Chip Power Delivery by Inductive Coupling with Ripple Canceling Scheme
- Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications
- A 4-10bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS with Wide Supply Voltage Range SAR Controller
- An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40nm CMOS
- Symbol-Rate Clock Recovery for Integrating DFE Receivers
- A 3Gbps Non-Contact Inter-Module Link with Twofold Transmission Line Couplers and Low Frequency Compensation Equalizer (Special Issue : Solid State Devices and Materials)
- Hybrid Speaker Recognition Using Universal Acoustic Model