A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology

概要

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The accuracy of the comparator, which is often determined by its offset, is essential for the resolution of the high performance mixed-signal system. Various design efforts have been made to cancel or calibrate the comparator offset due to many factors like process variations, device thermal noise and input-referred supply noise. However, effective and simple method for offset cancel by applying additional circuits without scarifying the power, speed and area is always challenging. This work explores a dynamic offset control technique that employs charge compensation by timing control. The charge injection and clock feed-through by the latch reset transistor are investigated. A simple method is proposed to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates. Further analysis for the principle of timing based charge compensation approach for comparator offset control is described. The analysis has been verified by fabricating a 65nm CMOS 1.2V 1GHz comparator that occupies 25×65µm2 and consumes 380µW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.
（社）電子情報通信学会の論文
2010-12-01