0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS
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概要
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In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDOs, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.
- 2011-06-01
著者
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ISHIDA Koichi
The University of Tokyo
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Takamiya Makoto
Institute Of Industrial Science The University Of Tokyo
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Sakurai Takayasu
Institute Of Industrial Science The University Of Tokyo
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Sakurai Takayasu
Institute Of Industrial Science & Center For Collaborative Research The University Of Tokyo
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Chen Po-hung
The University Of Tokyo
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Okuma Yasuyuki
Semiconductor Technology Academic Research Center (starc)
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Zhang Xin
The University Of Tokyo
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Ryu Yoshikatsu
Semiconductor Technology Academic Research Center (STARC)
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WATANABE Kazunori
Semiconductor Technology Academic Research Center (STARC)
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CHEN Po-Hung
Institute of Industrial Science, The University of Tokyo
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Zhang Xin
Institute For Horticultural Plants China Agricultural University
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Ishida Koichi
Institute Of Industrial Science The University Of Tokyo
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