A-3-9 Low-Energy Flip-Flops Using Transistor Stacking Effect
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概要
- 論文の詳細を見る
In order to maintain the historical trend in delay reduction, technology downsizing imposes a continuous decrease in both V_<dd> and V_<th>. However, The leakage current increases substantially when V_<th> is reduced and consequently leakage power is becoming an important element of the total consumed power. In this paper, we propose a novel Flip-Flop, called stacking effect Flip-Flop (SEFF), and based on the C^2MOS-FF. In the proposed Flip-Flop We take advantage of the leakage current reduction that occurs when stacked off-off MOS devices are used. Moreover, the impact of the added stack MOS devices on the delay and stability of the SEFF are also discussed. Our analysis is based on the simulation results of 65nm CMOS technology node (Berkeley Predictive Technology model).
- 社団法人電子情報通信学会の論文
- 2003-09-10
著者
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Sakurai Takayasu
Institute Of Industrial Science & Center For Collaborative Research The University Of Tokyo
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Sakurai Takayasu
Institute Of Industrial Sciences University Of Tokyo
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Fayez Robert
Institute Of Industrial Sciences University Of Tokyo
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