A-3-15 POWER CONSUMPTION DISTRIBUTION IN DSM INTERCONNECTS WITH INDUCTIVE EFFECTS

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概要

• 論文の詳細を見る
• 社団法人電子情報通信学会の論文
• 2003-03-03

著者

• SAKURAI Takayasu

  Institute of Industrial Science, The University of Tokyo

• Sakurai Takayasu

  Institute Of Industrial Science & Center For Collaborative Research The University Of Tokyo

• Sakurai Takayasu

  Institute Of Industrial Science University Of Tokyo

• Antono D

  東大 生産技研

• Antono Danardono

  Institute Of Industrial Science The University Of Tokyo:(present Office)sony Corporation

• Antono Danardono

  Institute Of Industrial Science The University Of Tokyo

関連論文

• A 1.76mW, 100Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS
• A 100Mbps, 4.1pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90nm CMOS
• Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)
• Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's(Interconnect,VLSI Design and CAD Algorithms)
• A 1.76mW, 100Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS
• A-3-15 POWER CONSUMPTION DISTRIBUTION IN DSM INTERCONNECTS WITH INDUCTIVE EFFECTS
• Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines(Physical Design,VLSI Design and CAD Algorithms)
• Trends of On-Chip Interconnects in Deep Sub-Micron VLSI (Interconnect Technique, VLSI Design Technology in the Sub-100nm Era)
• Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-V_SRAM's(Electronic Circuits)
• サブ1VのSRAMにおけるリークを2桁以上削減する新手法RRDSV(システムLSIの応用とその要素技術,専用プロセッサ,プロセッサ,DSP,画像処理技術,及び一般)
• サブ1VのSRAMにおけるリークを2桁以上削減する新手法RRDSV(システムLSIの応用とその要素技術,専用プロセッサ,プロセッサ,DSP,画像処理技術,及び一般)
• サブ1VのSRAMにおけるリークを2桁以上削減する新手法RRDSV(システムLSIの応用とその要素技術,専用プロセッサ,プロセッサ,DSP,画像処理技術,及び一般)
• Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques
• A-3-9 Low-Energy Flip-Flops Using Transistor Stacking Effect
• A charge-domain auto- and cross-correlation based IR-UWB receiver with power- and area-efficient PLL for 62.5ps step data synchronization in 65nm CMOS (集積回路)
• A-3-7 Inductance Effect on VLSI Interconnections
• 0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications
• 0.6V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver
• 0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS
• EMI Camera LSI (EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution
• Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)
• Optimum Device Consideration for Standby Power Reduction Scheme Using Drain-Induced Barrier Lowering
• Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

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