Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques
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概要
- 論文の詳細を見る
VLSIの消費電力の多くの部分を消費しているクロックシステムの低消費電力化は重要な課題である。本論文では、低クロック電圧振幅を用いて低電力化するために必須である、低クロック振幅対応のフリップフロップ回路を提案する。従来と違い、基板バイアスに頼らず、contentionを減少させるメカニズムを導入することにより、低クロック振幅での遅延と消費電力が、それぞれ、従来比30%、20%小さいことがシミュレーションにより示された。
- 社団法人電子情報通信学会の論文
- 2005-12-09
著者
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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Sakurai Takayasu
Univ. Tokyo Tokyo Jpn
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Sakurai Takayasu
Institute Of Industrial Science & Center For Collaborative Research The University Of Tokyo
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Kawaguchi Hiroshi
Department Of Computer Science And Systems Engineering Kobe University
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Kawaguchi Hiroshi
Institute Of Industrial Science The University Of Tokyo:(present Office)kobe University
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Yazid Muhammad
Institute of Industrial Science & Center for Collaborative Research, The University of Tokyo
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Yazid Muhammad
Institute Of Industrial Science & Center For Collaborative Research The University Of Tokyo
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Kawaguchi Hiroshi
Institute Of High Speed Mechanics Tohoku University
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