Area Comparison between 6T and 8T SRAM Cells in Dual-V_<dd> Scheme and DVS Scheme(Memory Design and Test,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper compares areas between a 6T and 8T SRAM cells, in a dual-V_<dd> scheme and a dynamic voltage scaling (DVS) scheme. In the dual-V_<dd> scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the area.

• 社団法人電子情報通信学会の論文
• 2007-12-01

著者

• Iguchi Yusuke

  Kobe Univ. Kobe‐shi Jpn

• Nii Koji

  Kobe University:renesas Technology Corporation

• Noguchi Hiroki

  Kobe University

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• Kawaguchi Hiroshi

  Kobe Univ. Kobe‐shi Jpn

• Nii Koji

  Kobe University

• Morita Yasuhiro

  Department Of Computer Science And Systems Engineering Kobe University

• YOSHIMOTO Masahiko

  Kobe University

• FUJIWARA Hidehiro

  Kobe University

• MORITA Yasuhiro

  Kobe University

• Kawaguchi Hiroshi

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

• FUJIWARA Hidehiro

  the Graduate School of Science and Technology, Kobe University

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