A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, <Special Section>Low-Power LSI and Low-Power IP)

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概要

• 論文の詳細を見る

• This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ringconnected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45-73% in comparison to cases with conventional architectures for motion estimation.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• Miyama Masayuki

  Kanazawa University Graduate School Of Natural Science & Technology

• Miyama M

  Graduate School Of Natural Science And Technology Kanazawa University

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• Morita Yasuhiro

  Department Of Computer Science And Systems Engineering Kobe University

• MIYAKOSHI Junichi

  Kobe University

• Matsuno Tetsuro

  Kanazawa University Graduate School Of Natural Science & Technology

• Yoshimoto Masahiko

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• Yoshimoto Masahiko

  Faculty Of Engineering Kobe University

• Hamano Koji

  Faculty Of Engineering Kanazawa University

• MURACHI Yuichiro

  Faculty of Engineering, Kanazawa University

• MATSUNO Tetsuro

  Faculty of Engineering, Kanazawa University

• MIYAKOSHI Junichi

  Faculty of Engineering, Kobe University

• MIYAMA Masayuki

  Faculty of Engineering, Kanazawa University

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

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