A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI
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概要
- 論文の詳細を見る
This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition. We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. Measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02× and 2.25× times faster than real-time at 200 MHz using the bigram and trigram language models, respectively.
- The Institute of Electronics, Information and Communication Engineersの論文
著者
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Miyamoto Yuki
Department Of Biology Faculty Of Science Chiba University
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Yoshimoto Masahiko
Department Of Computer Science And Systems Engineering Kobe University
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Izumi Shintaro
Department Of Computer Science And Systems Engineering Kobe University
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Kawaguchi Hiroshi
Department Of Applied Chemistry Faculty Of Engineering Utsunomiya University
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Yoshimoto Masahiko
Department of Information Science, Kobe University
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He Guangji
Department of Information Science, Kobe University
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Matsuda Kumpei
Department of Information Science, Kobe University
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Yoshimoto Masahiko
Department of Computer and Systems Engineering, Kobe University
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Izumi Shintaro
Department of Information Science, Kobe University
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- A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI