Area Optimization in 6T and 8T SRAM Cells Considering V_<th> Variation in Future Processes(Next-Generation Memory for SoC,<Special Section>VLSI Technology toward Frontiers of New Market)

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概要

• 論文の詳細を見る

• This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.

• 社団法人電子情報通信学会の論文
• 2007-10-01

著者

• Iguchi Yusuke

  Kobe Univ. Kobe‐shi Jpn

• Nii Koji

  Kobe University:renesas Technology Corporation

• Noguchi Hiroki

  Kobe University

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• Kawaguchi Hiroshi

  Kobe Univ. Kobe‐shi Jpn

• Nii Koji

  Kobe University

• Morita Yasuhiro

  Department Of Computer Science And Systems Engineering Kobe University

• YOSHIMOTO Masahiko

  Kobe University

• FUJIWARA Hidehiro

  Kobe University

• MORITA Yasuhiro

  Kobe University

• Kawaguchi Hiroshi

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

• FUJIWARA Hidehiro

  the Graduate School of Science and Technology, Kobe University

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