YOSHIMOTO Masahiko | Kobe University

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概要

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著作論文

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
A Dependable SRAM with 7T/14T Memory Cells
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
Area Comparison between 6T and 8T SRAM Cells in Dual-V_ Scheme and DVS Scheme(Memory Design and Test,VLSI Design and CAD Algorithms)
Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE802.11e WLANs(Network)
A New Scheduler to Guarantee Delay Bound with Bandwidth Optimization for HCCA in IEEE 802.11e WLANs(QoS及びトラヒック管理(2),ユビキタスネットワーク,モバイルネットワーク及び一般)
A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition
VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells
A Sub-100mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
A 168-mW 2.4×-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells
A Sub-100mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
A 168-mW 2.4×-Real-Time 60-k Word Continuous Speech Recognition Processor VLSI

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