YOSHIMOTO Masahiko | Kobe University

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概要

• Yoshimoto Masahikoの詳細を見る
• 同名の論文著者
• Kobe Universityの論文著者

関連著者

• YOSHIMOTO Masahiko

  Kobe University

• Kawaguchi Hiroshi

  Kobe Univ. Kobe‐shi Jpn

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• Kawaguchi Hiroshi

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• MORITA Yasuhiro

  Kobe University

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  Department Of Computer Science And Systems Engineering Kobe University

• Noguchi Hiroki

  Kobe University

• Morita Yasuhiro

  Department Of Computer Science And Systems Engineering Kobe University

• FUJIWARA Hidehiro

  Kobe University

• OKUMURA Shunsuke

  Kobe University

• IZUMI Shintaro

  Kobe University

• FUJIWARA Hidehiro

  the Graduate School of Science and Technology, Kobe University

• Iguchi Yusuke

  Kobe Univ. Kobe‐shi Jpn

• YOSHIMOTO Shusuke

  Kobe University

• Nii Koji

  Kobe University:renesas Technology Corporation

• Nii Koji

  Kobe University

• SUGAHARA Takanobu

  Kobe University

• MIZUNO Kosuke

  Kobe University

• HE Guangji

  Kobe University

• TERACHI Yosuke

  Kobe University

• MURACHI Yuichiro

  Kobe University

• MIYAKOSHI Junichi

  Kobe University

• Ohta Chikara

  Kobe Univ. Kobe‐shi Jpn

• FORONDA Augusto

  Faculty of Engineering, Kobe University

• HIGUCHI Yuhi

  Faculty of Engineering, Kobe University

• OKADA Yoji

  Information and Communication Laboratories, Sumitomo Electric Industries

• Foronda Augusto

  Faculty Of Engineering Kobe University

• Okada Yoji

  Information And Communication Laboratories Sumitomo Electric Industries

• Higuchi Yuhi

  Faculty Of Engineering Kobe University

• MIURA Kazuo

  Kobe University

• FUJINAGA Tsuyoshi

  Kobe University

• YAMAGUCHI Kosuke

  Kobe University

• MIYAMOTO Yuki

  Kobe University

• TAKAGI Kenta

  Kobe University

• YOSHIMOTO Masahiko

  Department of Computer Science and Systems Engineering, Kobe University

• Ohta Chikara

  Faculty Of Engineering Kobe University

• Ohta Chikara

  Faculty Of Engineering Gunma University:(present Address)university Of Tokushima

• Miyama Masayuki

  Kanazawa University Graduate School Of Natural Science & Technology

• Miyama M

  Graduate School Of Natural Science And Technology Kanazawa University

• Miyama Masayuki

  Kanazawa Univ. Kanazawa‐shi Jpn

• Yamamoto Ryo

  Kobe University

• FUKUYAMA Yuki

  Kobe University

• ISHIHARA Hajime

  Kanazawa University

• MATSUDA Yoshio

  Kanazawa University

• Ohta Chikara

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  Faculty Of Engineering Kobe University

• HAMAMOTO Masaki

  Kobe University

• IINUMA Takahiro

  Kobe University

• ISHIHARA Tomokazu

  Kobe University

• YIN Fang

  Kobe University

• LEE Jangchung

  Kobe University

• Izumi Shintaro

  Department Of Computer Science And Systems Engineering Kobe University

• Ariki Yasuo

  Kobe Univ. Kobe‐shi Jpn

• Higuchi Yuhi

  Department of Computer System, Kobe University

• Foronda Augusto

  Department of Computer System, Kobe University

• Ohta Chicara

  Department of Computer System, Kobe University

• Ishihara Hajime

  Kanazawa Univ. Kanazawa‐shi Jpn

• Kawaguchi Hiroshi

  Kobe University

• KAMINO Tetsuya

  Kobe University

• Ariki Yasuo

  Kobe University

• NAKATA Yohei

  Kobe University

• Ohta Chikara

  Department of Computer and Systems Engineering, Kobe University

• Yoshimoto Masahiko

  Department of Computer and Systems Engineering, Kobe University

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著作論文

• A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
• A Dependable SRAM with 7T/14T Memory Cells
• A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
• Area Comparison between 6T and 8T SRAM Cells in Dual-V_ Scheme and DVS Scheme(Memory Design and Test,VLSI Design and CAD Algorithms)
• Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
• A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
• Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE802.11e WLANs(Network)
• A New Scheduler to Guarantee Delay Bound with Bandwidth Optimization for HCCA in IEEE 802.11e WLANs(QoS及びトラヒック管理(2),ユビキタスネットワーク,モバイルネットワーク及び一般)
• A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition
• VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition
• A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
• A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
• A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
• A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells
• A Sub-100mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
• A 168-mW 2.4×-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI
• A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells
• A Sub-100mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
• A 168-mW 2.4×-Real-Time 60-k Word Continuous Speech Recognition Processor VLSI

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