OKUMURA Shunsuke | Kobe University

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概要

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著作論文

A Dependable SRAM with 7T/14T Memory Cells
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells
Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells

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