AMASHITA Takuro | Kobe University
スポンサーリンク
概要
関連著者
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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OKUMURA Shunsuke
Kobe University
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YOSHIMOTO Shusuke
Kobe University
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AMASHITA Takuro
Kobe University
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YOSHIMOTO Masahiko
JST CREST
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Nii Koji
Renesas Electronics Corporation
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YOSHIMOTO Masahiko
JST, CREST
著作論文
- Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
- Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
- Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure