YOSHIMOTO Masahiko | JST CREST

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概要

• YOSHIMOTO Masahikoの詳細を見る
• 同名の論文著者
• JST CRESTの論文著者

関連著者

• Kawaguchi Hiroshi

  Kobe Univ. Kobe‐shi Jpn

• YOSHIMOTO Shusuke

  Kobe University

• YOSHIMOTO Masahiko

  JST CREST

• OKUMURA Shunsuke

  Kobe University

• AMASHITA Takuro

  Kobe University

• Nii Koji

  Renesas Electronics Corporation

著作論文

• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
• Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
• Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell

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