FUJIWARA Hidehiro | the Graduate School of Science and Technology, Kobe University

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概要

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著作論文

A Dependable SRAM with 7T/14T Memory Cells
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
Area Comparison between 6T and 8T SRAM Cells in Dual-V_ Scheme and DVS Scheme(Memory Design and Test,VLSI Design and CAD Algorithms)
Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes
A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme

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