IINUMA Takahiro | Kobe University
スポンサーリンク
概要
関連著者
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Yoshimoto Masahiko
Mitsubishi Electric Corporation
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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Morita Yasuhiro
Department Of Computer Science And Systems Engineering Kobe University
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MIYAKOSHI Junichi
Kobe University
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MORITA Yasuhiro
Kobe University
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Kawaguchi Hiroshi
Department Of Computer Science And Systems Engineering Kobe University
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Yoshimoto Masahiko
Department Of Computer Science And Systems Engineering Kobe University
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Yoshimoto Masahiko
System Lsi Development Center Mitsubishi Electric Corporation
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HAMAMOTO Masaki
Kobe University
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IINUMA Takahiro
Kobe University
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ISHIHARA Tomokazu
Kobe University
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Yoshimoto M
Department Of Computer Science And Systems Engineering Kobe University
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Miyama Masayuki
Graduate School of Natural Science, Kanazawa University
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Kawaguchi Hiroshi
Graduate School of Engineering, Kobe University
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Yoshimoto Masahiko
Graduate School of Engineering, Kobe University
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Miyama Masayuki
Kanazawa University Graduate School Of Natural Science & Technology
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Miyama M
Graduate School Of Natural Science And Technology Kanazawa University
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Miyama Masayuki
Graduate School Of Natural Science And Technology Kanazawa Univ.
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MURACHI Yuichiro
Kobe University
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YOSHIMOTO Masahiko
Kobe University
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Matsuno Tetsuro
Kanazawa University Graduate School Of Natural Science & Technology
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Matsuno Tetsuro
Graduate School Of System Informatics Kobe University
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YIN Fang
Kobe University
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LEE Jangchung
Kobe University
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MIYAKOSHI Junichi
Graduate School of Science and Technology, Kobe University
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MURACHI Yuichiro
Graduate School of Science and Technology, Kobe University
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HAMAMOTO Masaki
Graduate School of Science and Technology, Kobe University
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IINUMA Takahiro
Graduate School of Science and Technology, Kobe University
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ISHIHARA Tomokazu
Graduate School of Science and Technology, Kobe University
著作論文
- A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
- A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture